1. Field of the Invention:
The present invention relates to data processing systems utilizing cache memories, and more particularly, to microprocessor based systems utilizing an external cache; that is, a cache that is external to the integrated circuit that comprises the microprocessor.
2. Art Background:
It is common in many data processing systems to utilize a high speed buffer memory, referred to as a "cache", coupled to a central processing unit (CPU) to improve the average memory access time for the processor. The use of a cache is based upon the premise that over time, a data processing system will access certain localized areas of memory with high frequency. The cache typically contains a subset of the complete data set disposed in the main memory, and can be accessed very quickly by the CPU without the necessity of reading the data locations in the main memory.
A historic problem with cache systems is access time as a function of system clock cycles. Although cache systems are, by nature, faster than non-cache systems when the data desired is in fact located in the cache, the time required for the cache access can be significant. This is particularly true when the external cache is very large and presents a large capacitive load to the address bus of the processor. The driving of such large external, capacitive loads is a problem in many microprocessors based systems. However, such large caches are desirable since they result in fewer misses and thus faster execution of programs.
As will be described, the present invention provides an improved interface between the processor and the external cache which allows for a shorter access time and a larger cache than otherwise would be possible The present invention:
(1) utilizes inherent delays in the receipt of clock signals to provide additional time for cache access, thereby allowing for a shorter processor cycle time and a correspondent increase in the speed that the processor can execute instructions;
(2) allows the cache to be larger than it otherwise could be for short cache access times A short cycle time is achieved even though the cache presents a large capacitive load to the memory address bus of the processor.